MSP430 Architecture

Msp 430 Architecture Click Here

The micro-controller's performance is directly related to the 16-bit data bus, the 7 addressing modes and the reduced instructions set, which allows a shorter, denser programming code for fast execution. These micro-controller families share a 16-bit CPU (Central Processing Unit) core, RISC1 type, intelligent peripherals, and flexible clock system that interconnect using a Von Neumann2 common memory address bus (MAB) and memory data bus (MDB) architecture.

MSP430 Architecture

RISC (Reduced Instructions Set Computing) – In this type of configuration, the instructions are reduced to the basic ones, with the objective of providing simpler and faster instruction decoding. The MSP430 only uses 27 physical instructions and 24 emulated instructionsVon Neumann architecture - Computational architecture that makes use of only one storage structure to save the data and instructions sets. In the model, the separation of the processing unit storage is implicit. Since the instructions are treated as data, the devices that use this type of architecture can easily modify the instruction, i.e., are programmable.